1. Field of the Invention
The present invention relates to logic gate cells used as an element in an LSI designed in a standard cell format and falls within the layout design technology of the logic gate cell manufactured in CMOS processes, and particularly to a logic gate cell featuring a small area and low power consumption.
2. Description of the Related Art
A cell having a circuit arrangement of two inverting logic gates connected is frequently used for a logic gate cell that is an element when an LSI is designed using a standard cell technology. The inverting logic gates here refer to a NAND gate, a NOR gate, a NOT gate, an AND-NOR compound gate and an OR-NAND compound gate. Logic symbols and circuit examples corresponding to the inverting logic gates are respectively shown in FIGS. 1A and 1B through FIGS. 7A and 7B. FIGS. 1A through 7A respectively show the logic symbols and FIGS. 1B through 7B respectively show the circuit examples thereof. Referring to a two-input AND gate as a typical example of these gates, the conventional art of the layout of the logic gate cell is now discussed.
The logic symbol of the two-input AND gate AND2 is shown in FIG. 8A and the two-input AND gate AND2 is constructed by configuring an inverting logic gate NAND2 and a NOT as shown in FIG. 8B, and an example of the circuit is shown in FIG. 9. FIG. 10 shows a conventional layout example of gate NAND2. FIG. 11 shows diffusion regions and polysilicon wirings extracted from the layout shown in FIG. 10, FIG. 12 shows first metal layer wirings extracted from the layout shown in FIG. 10, and FIG. 13 shows second metal layer wirings extracted from the layout shown in FIG. 10. A diffusion region 501 for forming a P-type MOS transistor is arranged within a well 19, and a diffusion region 502 for forming an N-type MOS transistor is arranged outside and below the well 19. Transistors are formed at intersections where gate polysilicon wirings 503 intersect the diffusion regions 501 and 502. P-type MOS transistors 31 to 33 shown in FIG. 9 are formed side by side horizontally on the diffusion region 501 as shown in FIGS. 10 and 11, and N-type MOS transistors 34 to 36 shown in FIG. 9 are formed side by side horizontally on the diffusion region 502 as shown in FIGS. 10 and 11. Squares shown in FIG. 10, FIG. 12 and FIG. 13 represent contacts and via holes.
Available as methods of reducing the power consumption of LSIs through design effort of the logic gate cell are a technique to narrow a gate width of a transistor to reduce the power consumption in a transistor portion and a technique to reduce a layout area of the logic gate cell to reduce metal wiring length, and thus to reduce static capacitance of a metal wiring section, and both techniques are used in combination. Common techniques to promote a low power consumption are discussed in more detail in "Technical Paper of Low-Power LSI (Nikkei Micro Device Issue, Nikkei BP Company in Japan)". In the gate AND2 cell, to narrow the gate width of the transistor, the height of the diffusion regions 501 and 502 (the vertical length in FIGS. 10 and 11) should be small. The reduction in the height of the diffusion regions serves as a reduction in the cell height (the vertical length in FIG. 10), and the cell area is accordingly reduced.
The above methods present the following problems. Firstly, when the cell height is lowered to reduce the cell area in the above methods, only the reduction in the height of the diffusion regions 501 and 502 contributes to lowering the cell height, and wiring areas other than the cell height and the spacing (a certain spacing is required in a region where the P-type changes to the N-type) between the diffusion region 501 and the diffusion region 502 are not reduced. As a result, as the cell area is reduced more, the area of the transistor portion gets smaller relative to the cell area, and the cell suffers a smaller area utilization. Secondly, as the cell height is lowered, there is no choice but to arrange a plurality of transistors horizontally side by side and connect them, to realize a high-power (wide gate width) transistor, and a horizontally elongated cell results, suffering a poor area utilization and the cell area, on the contrary, increases more than that in the high cell height layout. These problems arise as a result of attempting lower the cell height to reduce the cell area.